Power supply circuits within modern integrated circuit (IC) devices are often required to generate a constant, stable output voltage, typically from a varying input voltage. For example, in automotive applications a power supply circuit may be required to generate a regulated 7V output voltage from an input voltage from a battery comprising a voltage level ranging from, say, a nominal battery voltage of 14V down to 2.5V. Thus, low drop out voltage regulator circuits that provide a regulated supply voltage to circuits and functions have become popular.
With respect to LDO voltage regulator circuits, GO2 is an NMOS or PMOS device of the process, with significantly thicker gate oxide. These devices can therefore withstand high voltages, with ultra-low leakage. It is generally a large device, and the digital cells using it can be up to ten times larger than the standard cells (i.e., using GO1 devices that use regular gate thickness).
Voltage regulator circuits are now often used in ‘Internet of Things’ (IoT) devices. Voltage regulator circuits are also often used in ‘connected devices’, which is a term that is used to describe a device connected to a network via a radio frequency (RF) communication protocol, like ZigBee™, Bluetooth™, or any other radio protocol. A connected device is generally powered by a battery, which has a limited life time, depending on the current consumption of the said connected device. As a result, the lower the current consumption, the longer the device life time, and this has led to use of LDO supply voltages.
These connected devices spend most of their time waiting for an event that is triggered externally (e.g: a temperature sensor sending out its data, say, once a day, to a network, or a connected switch that sends out its data to a connected bulb, say, once in a while, or a home alarm system with a remote control that sends out its data to the alarm centre). These are some of the IoT use cases, mostly requiring a ‘nearly-always-off’ state, which is often referred to as a Deep Power Down (DPD) mode.
As a consequence, the current consumption whilst in DPD mode mostly determines the battery lifetime. Hence, it is necessary to minimize the current consumption of the circuits and functional blocks that still need to ensure some state retention in this mode, typically referred to as ‘always-on’ circuits and functional blocks.
Dependent upon the process node, it is not always possible to benefit from very low leakage digital libraries (generally using GO2 devices), and as a result GO1-based digital cells have to be used. When supplied with their nominal voltage (e.g. 1.1V in a 40 nm process), they are known to ‘leak’ current much more than the IoT standard allows. This is especially the case when the digital design represents a relatively large number of cells, e.g. large enough to impact the total current consumption due to the cells' leakage. A way to drastically reduce this leakage is to decrease the supply voltage down to a minimum value, under which retention may become erratic.
The only way to control properly the supply voltage to these always-on digital cells is to use an ‘always-on’ LDO, which itself has to consume a very small part of the current budget. Though weakly biased, such LDOs have to firmly maintain their regulated output close to a regulation target in order not to endanger the circuits and functional blocks that they supply, irrespective of the load current transitions.
FIG. 1 illustrates a conventional LDO output response 100 to an increase in different load current from line 145 to line 140. The LDO output response 100 illustrates target output voltage 110 and current load (Iload) 115 versus time 120. It is known by those skilled in the art that the reaction time Δt of an LDO is inversely proportional to its regulation bandwidth. When the biasing current is very low, then the reaction time is very high. As a consequence, any abrupt increase of the load current (e.g. from 145 to 140) will make the output voltage drop (from 130 to 135) until the feedback loop in the voltage regulator counteracts it and returns the LDO voltage back to the target voltage 125, as illustrated in FIG. 1.
The equation that basically provides the voltage drop ΔV at the output of a conventional LDO is the following:Iload*Δt=Cload*ΔV,  [1]With:                Iload identifying the average load current;        Δt identifying the reaction time of the LDO; and        Cload identifying the decoupling capacitor value of the LDO.        
When using biasing currents that are too small, the bandwidth of the LDO becomes so small that Δt becomes very high. Thus, any sudden Iload increase turns into an uncompensated drop at the LDO output, at least temporarily. In addition, a digital design does not demand a constant current to its supply, and as such there can be sudden current peaks linked to the digital activity. It can easily be figured out by a person skilled in the art that the output of a conventional weakly biased LDO will not be regulated well with this type of varying load current. An improved voltage regulator circuit and a method of regulating a voltage in response to rapid changes of load current are required.
In the publication titled ‘Ultralow-power fast-transient output-capacitor-less low-dropout regulator with advanced adaptive biasing circuit’, authored by Xi Qu et al, and published in IET Circuits, Devices & Systems, 2015, the authors' proposed design focused on the ability to react quickly to a current decrease. In essence, the authors propose to use the output current information, not the regulated output itself. This publication does not consider any effect of, or propose any solution to, a fast current increase. The inventor of the present invention has recognised and appreciated that this publication also does not consider true zero load current to high load current transients.
In the publication titled ‘An Output-Capacitor-less Low-Dropout Regulator With Direct Voltage-Spike Detection’, authored by Pui Ying Or and Ka Nang Leung, and published in IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. 45, NO. 2, FEBRUARY 2010, the authors' proposed design includes a dynamic compensation of the LDO when voltage spikes occur at the LDO output. Notably, this design is tightly linked to a specific LDO topology (i.e. a PMOS output stage). The dynamic compensation of the design specifically, and solely, occurs for a fixed time after the spike event and has quiescent currents in the range of tens of μA.
In the publication titled ‘Adaptively-Biased Capacitor-Less CMOS Low Dropout Regulator with Direct Current Feedback’, authored by Yat-Hei Lam et al, and published in IEEE, 2006, the authors' proposed design is of a linear output load current adaptive biasing scheme. Notably, it is unsuitable for an ultra-low power design, as a lot of current hungry circuitry is needed, and, not least that the design requires ˜3 μA @ zero load current.